The present invention relates generally to flash memory cell devices and more specifically, to improvements in pre-charge systems for reducing short channel current leakage during programming of a dual bit dielectric memory cell structure.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a xe2x80x9creadxe2x80x9d of the memory cell, the programmed, or non-programmed, state of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently dielectric memory cell structures have been developed. A conventional array of dielectric memory cells 10a-10f is shown in cross section in FIG. 1. Each dielectric memory cell is characterized by a vertical stack of an insulating tunnel layer 18, a charge trapping dielectric layer 22, an insulating top oxide layer 24, and a polysilicon control gate 20 positioned on top of a crystalline silicon substrate 15. Each polysilicon control gate 20 may be a portion of a polysilicon word line extending over all cells 10a-10f such that all of the control gates 20a-20g are electrically coupled.
Within the substrate 15 is a channel region 12 associated with each memory cell 10 that is positioned below the vertical stack. One of a plurality of bit line diffusions 26a-26g separate each channel region 12 from an adjacent channel region 12. The bit line diffusions 26 form the source region and drain region of each cell 10. This particular structure of a silicon channel region 12, tunnel oxide 18, nitride 22, top oxide 24, and polysilicon control gate 20 is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell 10 is programmed by inducing hot electron injection from the channel region 12 to the charge trapping dielectric layer 22, such as silicon nitride, to create a non volatile negative charge within charge traps existing in the nitride layer 22. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate 20. The high voltage on the control gate 20 inverts the channel region 12 while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region 12 and the tunnel oxide 18. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region. For example, a charge can be stored in a drain bit charge storage region 16b of memory cell 10b. The bit line 26b operates as the source region and bit line 26c operates as the drain region. A high voltage may be applied to the channel region 20b and the drain region 26c while the source region 26b is grounded.
Similarly, a source-to-drain bias may be applied along with a high positive voltage on the control gate to inject hot electrons into a source charge storage region that is close to the source region. For example, grounding the drain region 26c in the presence of a high voltage on the gate 20b and the source region 26b may be used to inject electrons into the source bit charge storage region 14b. 
As such, the SONOS device can be used to store two bits of data, one in each of the source charge storage region 14 (referred to as the source bit) and the charge storage region 16 (referred to as the drain bit).
Due to the fact that the charge stored in the storage region 14 only increases the threshold voltage in the portion of the channel region 12 beneath the storage region 14 and the charge stored in the storage region 16 only increases the threshold voltage in the portion of the channel region 12 beneath the storage region 16, each of the source bit and the drain bit can be read independently by detecting channel inversion in the region of the channel region 12 between each of the storage region 14 and the storage region 16. To xe2x80x9creadxe2x80x9d the drain bit, the drain region is grounded while a voltage is applied to the source region and a slightly higher voltage is applied to the gate 20. As such, the portion of the channel region 12 near the source/channel junction will not invert (because the gate 20 voltage with respect to the source region voltage is insufficient to invert the channel) and current flow at the drain/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the drain bit.
Similarly, to xe2x80x9creadxe2x80x9d the source bit, the source region is grounded while a voltage is applied to the drain region and a slightly higher voltage is applied to the gate 20. As such, the portion of the channel region 12 near the drain/channel junction will not invert and current flow at the source/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the source bit.
In a typical flash memory array, the row and column structure creates problems when programming a selected cell. Each memory cell within a column shares a common source bit line and drain bit line with other memory cells within the column. As such, if other cells within the column leak current between the source bit line and the drain bit line when the drain to source bias is applied, the current leakage will reduce the magnitude of such bias thereby decreasing the programmed charge, can cause an unintended partial programming of unselected cells sharing the same bit lines, and can reduce programming speed, and increase programming current consumption. As memory array applications demand smaller memory cells structures, the short channel effects of the smaller cell structure increases the likelihood of a punch-through phenomena for the non-selected cells thereby exasperating the above described current leakage problems.
What is needed is an improved system for programming a dual bit dielectric memory cell that does not suffer the disadvantages of short channel current leakage.
A first aspect of the present invention is to provide array of dual bit dielectric memory cells that comprises programming systems that reduce programming current leakage through non-selected memory cells sharing the same column with selected memory cells.
The array comprises: i) a first bit line of a first conductivity semiconductor forming a source region for each of a plurality of memory cells within a column of memory cells within the array; and ii) a second bit line of the first conductivity semiconductor forming a drain region for each of the plurality of memory cells within the column, the second bit line separated from the first bit line by a semiconductor of the opposite conductivity forming a channel region for each of the e plurality of memory cells within the column.
The array further comprises a selected word line positioned over the channel region of a selected one of the plurality of memory cells within the column. The selected word line further forms a gate for each for a plurality of memory cells within a same row of the array as the selected memory cell. Each of a plurality of non-selected word lines, each parallel to the selected word line, form a gate over one of the plurality of non-selected memory cells within the column.
The array further comprises an array control circuit that includes a bit line control circuit, a word line control circuit, and a substrate potential control circuit. During programming of a drain charge trapping region of the selected memory cell, the word line control circuit may apply a positive programming voltage to the selected word line. In conjunction therewith, the bit line control circuit may apply: i) a positive drain voltage to the drain bit line; and ii) a positive source voltage to the source bit line with the positive source voltage being less than the positive drain voltage.
The positive source voltage may be between one tenth of the positive drain voltage and three tenths of the positive drain voltage. Or, to state a more narrow range, the positive source voltage may be between on one tenth of the positive drain voltage and two tenths of the positive drain voltage.
The array may further comprise a resistor coupled between the bit line control circuit and a ground. As such, the bit line control circuit may couple the source bit line to the resistor whereby the positive source voltage is equal to the voltage increase through the resistor.
The word line control circuit may further provide for applying a negative bias voltage to the non-selected word lines in conjunction with the applying a positive programming voltage to the selected word line. The negative bias voltage may be between xe2x88x920.1 volts and xe2x88x922.0 volts. Or, to state a more narrow range, the negative bias voltage may be between xe2x88x920.5 volts and xe2x88x921.0 volts.
The substrate voltage control circuit may provide for applying a negative substrate voltage to the substrate in conjunction with the word line control circuit applying a positive programming voltage to the selected word line. The negative substrate voltage may be between xe2x88x920.1 volts and xe2x88x922.0 volts. Or, to state a more narrow range, the negative substrate voltage may be between xe2x88x920.5 volts and xe2x88x921.0 volts.
A second aspect of the invention is to provide a method of programming a charge into a charge storage region of a selected dual bit dielectric memory cell within an array of dual bit dielectric memory cells. The array comprises a plurality of parallel bit lines forming a source and a drain for each cell and a plurality of parallel word lines forming a gate for each cell, the method comprises: i) applying a positive drain voltage to a first bit line that forms a drain junction with the channel region, the first bit line positioned to the right of a channel region; ii) applying a positive source voltage to a second bit line that forms a source junction with the channel region of the selected memory cell in conjunction with applying the positive drain voltage to the first bit line, the positive source voltage being less than the positive drain voltage and the channel region being to the right of the second bit line; and iii) applying a positive program voltage to a selected one of the word lines in conjunction with applying the positive drain voltage to the first bit line, the selected one of the word lines being the word line that forms a gate of the selected memory cell.
The positive source voltage may be between one tenth of the positive drain voltage and three tenths of the positive drain voltage. Or, to state a more narrow range, the positive source voltage may be between on one tenth of the positive drain voltage and two tenths of the positive drain voltage.
The method may further comprise coupling a resistor between the source bit line and ground. As such, the positive source voltage is equal to the voltage increase through the resistor.
The method may further comprise applying a negative bias voltage to the non-selected word lines in conjunction with the word line control circuit applying a positive programming voltage to the selected word line. The negative bias voltage may be between xe2x88x920.1 volts and xe2x88x922.0 volts. Or, to state a more narrow range, the negative bias voltage may be between xe2x88x920.5 volts and xe2x88x921.0 volts.
The method may further comprise applying a negative substrate voltage to the substrate in conjunction with the word line control circuit applying a positive programming voltage to the selected word line. The negative substrate voltage may be between xe2x88x920.1 volts and xe2x88x922.0 volts. Or, to state a more narrow range, the negative substrate voltage may be between xe2x88x920.5 volts and xe2x88x921.0 volts.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings. The scope of the invention is set forth in the appended dams.